/*
 * Copyright 2022 Rich yang, 18158898020@189.com
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     https://www.apache.org/licenses/LICENSE-2.0
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied,
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 */

`include "defines.v"

module if_id(
	input wire	clk,
	input wire	rst,
	input wire[`StallBus] stall,
	// source from fetch stage signal,
	input wire [`InstAddrBus] if_pc,
	input wire [`InstBus]	  if_inst,
	input wire 	flush_inst_i,

	// sink to decode stage
	output reg [`InstAddrBus] id_pc,
	output reg [`InstBus]	  id_inst
);

	always @ (posedge clk) begin
		if (rst == `RstEnable) begin
			id_pc   <= `ZeroWord;
			id_inst <= `ZeroWord;
		end else if (flush_inst_i == 1'b1) begin
			id_pc	<= `ZeroWord;
			id_inst	<= `ZeroWord;
		end else if (stall[1] == `Stop && stall[2] == `NoStop) begin
			id_pc	<= `ZeroWord;
			id_inst	<= `ZeroWord;
		end else if (stall[1] == `NoStop) begin
			id_pc   <= if_pc;
			id_inst <= if_inst;
		end
	end
endmodule
